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d-Matrix

3 min readUpdated November 2026
d-Matrix
Type
AI semiconductor company (inference compute)
Headquarters
Santa Clara, California, United States
Focus
Generative AI inference for data centres
First product
Corsair (shipped November 2024)
Funding
US$450 million total; US$2 billion valuation (Nov 2025)
Related
AI Accelerators, Inference, Groq, Cerebras Systems
d-Matrix is a Santa Clara–based semiconductor company that designs accelerators dedicated to AI inference — the phase where trained models actually serve responses to users — rather than model training. It argues that inference workloads, which are far more numerous and cost-sensitive than training, are poorly served by general-purpose GPUs, and builds chips that compute in or near memory to cut data movement.[1]

History

The company was funded early by investors including Microsoft's venture arm M12; a US$110 million Series B round included Microsoft, and by late 2024 total funding had passed US$160 million.[2] d-Matrix shipped its first chip, Corsair, in November 2024, with early customers testing sample silicon ahead of fuller shipments.[2]

On 12 November 2025 the company closed an oversubscribed US$275 million Series C at a US$2 billion valuation, bringing total capital raised to US$450 million, with investors spanning North America, Europe, Asia and the Middle East.[1] Product development has continued into 2026, including rack-scale inference systems built around its Raptor XPUs and integration with NVLink Fusion.[3]

Key Concepts

  • Inference-first design. Training runs once; inference runs constantly. d-Matrix optimises for the latency, throughput and cost of serving rather than for backpropagation.[1]
  • Compute-in-memory / dataflow. By performing calculations where data already resides, the architecture targets the "memory wall" — the energy and time lost moving weights between memory and processors.[4]
  • Company claims. d-Matrix states its full-stack platform delivers roughly 10× faster performance, 3× lower cost and 3–5× better energy efficiency than GPU-based systems for generative AI inference; these are vendor benchmarks, and independent verification is limited.[1]
  • Disaggregated serving. Rack-scale designs separate prefill and decoding stages so large-scale chatbot and video-generation services can be served more efficiently.[3]

Applications

Target workloads are chatbots, video and image generation, search and summarisation at consumer scale — services where the cost per token dominates the business model. The company competes with other inference-specialist chipmakers such as Groq, Cerebras and SambaNova, as well as with GPU vendors' own inference-optimised hardware.

>See Also

🇲🇾Malaysian Context

🇲🇾 Relevance to Malaysia: inference efficiency is the issue that matters most to Malaysia's AI ambitions. Inference chips lower the cost per query, which matters more than raw training power for a country focused on deploying AI in government, education and enterprise rather than training frontier models. Malaysia's data-centre boom in Johor and the Klang Valley is energy-constrained — more efficient inference per watt directly affects operating costs — while the National Semiconductor Strategy positions the country inside the chip supply chain through Penang's test, assembly and packaging ecosystem, which services precisely the kind of hardware d-Matrix produces.[5] Engineers should note that d-Matrix hardware is not widely deployed locally; Malaysian adoption today runs through NVIDIA-based clusters, so skills in optimised inference (quantisation, batching, KV-cache management) transfer more directly than vendor-specific tooling.[6]

References

  1. ↑d-Matrix. (2025). d-Matrix raises $275 million to power the age of AI inference. https://www.d-matrix.ai/announcements/d-matrix-raises-275-million-to-power-the-age-of-ai-inference/
  2. ↑Reuters, via d-Matrix. (2024). Microsoft-backed startup d-Matrix launches first AI chip. https://www.d-matrix.ai/announcements/microsoft-backed-startup-d-matrix-launches-first-ai-chip/
  3. ↑d-Matrix. (2026). Frontier class ultra-low-latency rack-scale inference with Raptor XPUs and NVLink Fusion. https://www.d-matrix.ai/frontier-class-ultra-low-latency-rack-scale-inference-with-raptor-xpus-and-nvlink-fusion/
  4. ↑d-Matrix. (2026). AI inference bottleneck: why it's memory, not compute. https://www.d-matrix.ai/ai-inference-bottleneck/
  5. ↑Government of Malaysia. National Semiconductor Strategy. https://www.mida.gov.my/
  6. ↑NVIDIA. Inference performance and optimization guidance. https://developer.nvidia.com/
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